Electrostatic charge is defined as “electric charge at rest”. Static electricity is an imbalance of electrical charges within or on the surface of a material. This imbalance of electrons produces an electric field that can be measured and that can influence other objects. Electrostatic discharge (ESD) is defined as the rapid, spontaneous transfer of electrostatic charge induced by a high electrostatic field. Electrostatic discharge can change the electrical characteristics of a semiconductor device, degrading or destroying it. As electronic devices become faster and smaller, their sensitivity to electrostatic discharge in general increases. This trend may be accelerating.
An ESD event will force a current pulse from few hundred milliamps to several tens of amps into the integrated circuit for a time period ranging from few nanoseconds to several microseconds. Typical power levels that need to be dissipated during an ESD event are on the order of several tens of watts. An ESD protection circuit can be used to shunt the ESD current through the unpowered IC along the intended ESD protection path, while clamping the voltage at a safe level, without causing any IC functional performance degradation. An ESD protection mechanism should therefore have the ability to protect the circuit and the components to which it is connected. This may include a fast turn-on of ESD protection device, which minimizes the voltage clamping level, and shunts ESD energy away from the protected circuit area.
To ensure a robust ESD protection design, ESD protection evaluation and verification needs to be done at every stage of an overall integrated circuit design flow. Today's electronic design automation tool landscape offers a wide range of options for rule-based ESD verification. For example, designers may identify the protection schemes, write a pattern template for each protection scheme as an input for a verification tool and run the verification tool to automatically identify whether these patterns are present on all input/output pads in a design.
Rule-based ESD verification can provide relatively fast analysis of an ESD protection design. As technology scaling continues, meeting product ESD targets becomes more challenging and requires a more comprehensive ESD verification methodology, however. In particular, time-domain analysis of ESD design cases requires simulation-based ESD verification. On the other hand, full-circuit simulation in SPICE (Simulation Program with Integrated Circuit Emphasis) is impractical given the large sizes of modern IC designs. It is also challenging for simulation-based ESD verification to utilize the vast amount of layout data present in a large design, which can lead to a more accurate and comprehensive analysis.